In 2002, Intel announced that it had developed a novel
three-dimensional design that will allow the manufacture of transistors
that scale, perform, and address the current leakage problem seen in
two-dimensional planar transistors. Tri-gate fully-depleted substrate
transistors have a raised plateau-like gate structure with two vertical
walls and a horizontal wall of gate electrode. This three-dimensional
structure improves the drive current while the depleted substrate
reduces the leakage current when the transistor is in the "off" state.
Reducing leakage current not only helps control heat at the circuit
level but also translates to increased battery life in mobile devices.
Intel's tri-gate technology surrounds the channel on three of four
sides, making it significantly more power efficient than either planar
or FinFET transistor technology (an alternative 3-D architecture that
has been proposed by IBM and others). The efficiency of the tri-gate
design is then enhanced by using both high-k gate insulators with metal
gates to improve both on and off currents, and adding strained silicon
for enhanced mobility (speed), further improving device performance.
In June 2006, Intel researchers announced the development of improved
CMOS tri-gate (3D) transistors, which are the first to integrate high-k
gate dielectrics and strained silicon to produce record drive currents
and transistor efficiency.
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In December 2005, researchers at Intel and QinetiQ announced the
development of a new, ultra-fast, yet very low power prototype
transistor using indium antimonide (chemical symbol: InSb) that could
form the basis of microprocessors and other logic products beginning in
the second half of the next decade. The prototype transistor is much
faster and consumes less power than previously announced transistors.
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