locked
Kernel Mode RRS feed

  • Question

  • If I understand correctly, any data structure (or pages) in the system space is only accessible when in kernel mode. The process's page directory resides in system space and whenever an address translation is required, the processor must be switched to kernel mode to access page directory?

    Similarly, when the scheduler starts thread dispatching logic, should it first change to kernel mode and start accessing the dispatcher database?

    Thanks,
    Suresh.
    Tuesday, November 10, 2009 6:49 PM

Answers

  • Suresh,

    You are right. If a TLB miss occurs, at least on x86 and probably x64 machines, the MMU does the page table walk on its own. It therefore facilitates the CR3 register (on x86) that contains the address of the page directory. The page directory must always be mapped into memory, so ther cannot be a page fault when accessing it. However, if a page table is referenced in the page directory that is not in memory, i.e. it's paged out, a page fault occurs and the OS has to map the page table back into memory. So basically the last instruction, the one that lead to the TLB miss in the first place is reexecuted, repeating the whole process.

    My fault here was that I mixed up the TLP with software managed TLB s that always trigger a page fault, when a TLB miss occurs.

    Sorry for the confusion :)

    Alex
    http://www.dcl.hpi.uni-potsdam.de/research/WRK
    Friday, November 13, 2009 8:46 AM

All replies

  • Hi Suresh,

    the memory management almost always encorporates a translation lookaside buffer (TLB) that caches the last VA-to-PA translation. So not every memory accesses leads to a new addres translation. However, if a virtual address is not in the TLB, i.e. a cache miss happenes, the memory management unit resolves the Physical Address (PA) from the page table. This happens as part of a page fault, which is a hardware interrupt. Whenever an interrupt fires, the processor automatically changes into kernel mode.

    The same is true for the scheduler. However, thread dispatching is only triggered from within the kernel. This is done either by a timer interrupt which is handled by the kernel anyway, or by executing some blocking IO, which is done through a system call which switches the processor into kernel mode already.

    Best regards,
    Alex

    http://www.dcl.hpi.uni-potsdam.de/research/WRK
    Thursday, November 12, 2009 9:32 PM
  • Hi Alex,

    Do you say a page fault occurs if the address is not in TLB? My understanding is that page fault occurs only when a page table (containing the referred address) is not constructed or the physical page is not in memory. Please confirm. If my understanding is correct and assuming the physical page is in memory, then the hardware must access page table to get the physical address. And the question is whether kernel mode transition is required to achive this or this is completely handled by MMU hardware?

    Thanks,
    Suresh.
    Thursday, November 12, 2009 10:57 PM
  • Suresh,

    You are right. If a TLB miss occurs, at least on x86 and probably x64 machines, the MMU does the page table walk on its own. It therefore facilitates the CR3 register (on x86) that contains the address of the page directory. The page directory must always be mapped into memory, so ther cannot be a page fault when accessing it. However, if a page table is referenced in the page directory that is not in memory, i.e. it's paged out, a page fault occurs and the OS has to map the page table back into memory. So basically the last instruction, the one that lead to the TLB miss in the first place is reexecuted, repeating the whole process.

    My fault here was that I mixed up the TLP with software managed TLB s that always trigger a page fault, when a TLB miss occurs.

    Sorry for the confusion :)

    Alex
    http://www.dcl.hpi.uni-potsdam.de/research/WRK
    Friday, November 13, 2009 8:46 AM
  • Thanks Alex.
    Saturday, November 14, 2009 9:06 PM
  • Alex,

    Another question regarding the transition.

    Will the stack pointer be pointing the kernel mode stack when (a thread) in kernel mode and point the user mode stack when in user mode?

    Thanks,
    Suresh.
    Tuesday, November 17, 2009 8:02 AM
  • Yes it is. When a thread transitions from one mode to another, the stack pointer will be adjusted appropriately.

    Alex

    http://www.dcl.hpi.uni-potsdam.de/research/WRK
    Tuesday, November 17, 2009 12:30 PM