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A lot of warnings during design optimization RRS feed

  • Question

  • Hello,

    I am currently trying to get the eMIPS running on a ml50x system, but I already have problems with the modelsim simulation of the functional model. I get a hole lot of warnings during design optimization. I have already tried to fix minor once like wrong with of busses tied to ground or the wrong size of the blockram. But the number of warnings is so huge that I thing maybe I am doing something wrong. Because there are over 200 warning I am only attaching the first once, so that the thread gets not flooded:

    # ** Note: (vsim-3812) Design is being optimized...
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/emips_platform.v(729): (vopt-2241) Connection width does not match width of port 'LED_OUT'. The port definition is at: ~/fpga/projects/emips/hdl/ml50x/../common/impl/serial_led/serial_led_switch.v(34).
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/ext_opc_cam.v(53): (vopt-2241) Connection width does not match width of port 'match_addr'. The port definition is at: ~/fpga/projects/emips/build_ml50x/generated/structural/extop_cam/extop_cam.v(37).
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/pipeline_arbiter2.v(243): (vopt-2241) Connection width does not match width of port 'WR_ADDR'. The port definition is at: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/extension_opcode_cam.v(37).
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/pipeline_arbiter2.v(262): (vopt-2241) Connection width does not match width of port 'CTRL_ADDR'. The port definition is at: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/ext_ctrl_regs.v(35).
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/priority_encoder.v(148): (vopt-2241) Connection width does not match width of port 'IN'. The port definition is at: ~/fpga/projects/emips/hdl/ml50x/../common/impl/components/multdetect9.v(28).
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/pipeline_arbiter2.v(307): (vopt-2241) Connection width does not match width of port 'CNTR_ADDR'. The port definition is at: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/extension_hit_counters.v(37).
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/pipeline_arbiter2.v(320): (vopt-2241) Connection width does not match width of port 'CNTR_ADDR'. The port definition is at: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/ext_interface/pipeline_arbiter/opcode_miss_counters.v(37).
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/ethernet/enic_mac.v(102): [TFMPC] - Too few port connections for 'v5_emac_wrapper'. Expected 41, found 33.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/ethernet/enic_mac.v(102): [TFMPC] - Missing connection for port 'EMAC0CLIENTTXSTATSBYTEVLD'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/ethernet/enic_mac.v(102): [TFMPC] - Missing connection for port 'EMAC0CLIENTTXSTATSVLD'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/ethernet/enic_mac.v(102): [TFMPC] - Missing connection for port 'EMAC0CLIENTTXSTATS'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/ethernet/enic_mac.v(102): [TFMPC] - Missing connection for port 'EMAC0CLIENTRXSTATSBYTEVLD'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/ethernet/enic_mac.v(102): [TFMPC] - Missing connection for port 'EMAC0CLIENTRXSTATSVLD'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/ethernet/enic_mac.v(102): [TFMPC] - Missing connection for port 'EMAC0CLIENTRXSTATS'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/ethernet/enic_mac.v(102): [TFMPC] - Missing connection for port 'EMAC0CLIENTRXFRAMEDROP'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/ethernet/enic_mac.v(102): [TFMPC] - Missing connection for port 'EMAC0CLIENTRXDVLDMSW'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/instruction_fetch/instruction_fetch.v(154): [TFMPC] - Too few port connections for 'add0'. Expected 5, found 4.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/instruction_fetch/instruction_fetch.v(154): [TFMPC] - Missing connection for port 'C_OUT'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/instruction_decode/instruction_decode.v(241): [TFMPC] - Too few port connections for 'shift0'. Expected 4, found 3.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/instruction_decode/instruction_decode.v(241): [TFMPC] - Missing connection for port 'C_OUT'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/instruction_decode/instruction_decode.v(249): [TFMPC] - Too few port connections for 'add0'. Expected 5, found 4.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/instruction_decode/instruction_decode.v(249): [TFMPC] - Missing connection for port 'C_OUT'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/execute/execute.v(270): [TFMPC] - Too few port connections for 'alu0'. Expected 16, found 15.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/execute/execute.v(270): [TFMPC] - Missing connection for port 'CARRY_OUT'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/execute/execute.v(287): [TFMPC] - Too few port connections for 'sh0'. Expected 4, found 3.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/pipeline/execute/execute.v(287): [TFMPC] - Missing connection for port 'C_OUT'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/datapath.v(805): [TFMPC] - Too few port connections for 'pa2'. Expected 38, found 35.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/datapath.v(805): [TFMPC] - Missing connection for port 'EXTSEN'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/datapath.v(805): [TFMPC] - Missing connection for port 'EXTKU'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/datapath.v(805): [TFMPC] - Missing connection for port 'EXTVP'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/datapath.v(1185): [TFMPC] - Too few port connections for 'ex'. Expected 38, found 37.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/datapath/datapath.v(1185): [TFMPC] - Missing connection for port 'ZERO'.
    ###### /poolroot/software/ise/12.4/ISE/verilog/src/unisims/ARAMB36_INTERNAL.v(851): 			   task_ram_col (web_tmp[2], wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[addra_tmp[14:5]][16 +: 8], memp[addra_tmp[14:5]][2]);
    # ** Warning: /poolroot/software/ise/12.4/ISE/verilog/src/unisims/ARAMB36_INTERNAL.v(851): [BSOB] - Bit-select into 'memp' is out of bounds.
    # ** Warning: /poolroot/software/ise/12.4/ISE/verilog/src/unisims/ARAMB36_INTERNAL.v(851): [BSOB] - Bit-select into 'memp' is out of bounds.
    ###### /poolroot/software/ise/12.4/ISE/verilog/src/unisims/ARAMB36_INTERNAL.v(855): 			   task_ram_col (web_tmp[3], wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[addra_tmp[14:5]][24 +: 8], memp[addra_tmp[14:5]][3]);
    # ** Warning: /poolroot/software/ise/12.4/ISE/verilog/src/unisims/ARAMB36_INTERNAL.v(855): [BSOB] - Bit-select into 'memp' is out of bounds.
    # ** Warning: /poolroot/software/ise/12.4/ISE/verilog/src/unisims/ARAMB36_INTERNAL.v(855): [BSOB] - Bit-select into 'memp' is out of bounds.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/memory_system/mmu/tlb_asid_lu.v(67): [TFMPC] - Too few port connections for 'tlbasc'. Expected 11, found 10.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/memory_system/mmu/tlb_asid_lu.v(67): [TFMPC] - Missing connection for port 'MATCH'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/memory_system/mmu/tlb_probe.v(131): [TFMPC] - Too few port connections for 'tlbc'. Expected 11, found 10.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/memory_system/mmu/tlb_probe.v(131): [TFMPC] - Missing connection for port 'BUSY'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/memory_system/mmu/tlb_probe.v(146): [TFMPC] - Too few port connections for 'tlbasc'. Expected 11, found 10.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/memory_system/mmu/tlb_probe.v(146): [TFMPC] - Missing connection for port 'BUSY'.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/memory_system/mmu/memory_management_unit2.v(227): [TFMPC] - Too few port connections for 'import'. Expected 34, found 33.
    # ** Warning: ~/fpga/projects/emips/hdl/ml50x/../common/impl/core/tisa/memory_system/mmu/memory_management_unit2.v(227): [TFMPC] - Missing connection for port 'INDEX'.

    Maybe this is a normal behavior, but I doubt it because the design seems not to execute code when I start the simulation. So I would be very happy if someone could give me a hint, what I am doing wrong.

    Regards

    Wednesday, July 13, 2011 2:17 PM