Actually i follow the tutorial and i arrive to 3.1.4 Synthesize the Top Level Module and i am in the step 5.
When i launch Synthesize - XST i obtain many errors like these
ERROR:NgdBuild:604 - logical block 'mips' with type 'TISA' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
case mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'TISA' is not supported in target 'virtex4'.
ERROR:NgdBuild:604 - logical block 'bmi13bm1' with type
'busmacro_xc4v_r2l_async_narrow' could not be resolved. A pin name
misspelling can cause this, a missing edif or ngc file, case mismatch between
the block name and the edif or ngc file name, or the misspelling of a type
name. Symbol 'busmacro_xc4v_r2l_async_narrow' is not supported in target
Can you help me about the source of these errors
What version of the sources are you using? V1 or V2? It appears you are using v1 since you are targeting a virtex 4. These are the type of errors you get you are missing sources. First double check your project hierarchy for these files.
Sorry i don't understand which version are you talking about ? The version of the macro_bus or what?
The version of the emips download. We released version 2 at the end of December.
No i have the version V1. Have i to move using the version V2.??
If you are targeting a v4 I would stay with version 1 for now. Version 2 is targeted at the v5 xup. It can be retargeted to the ml series v4 boards but I have done it in a while and the may be bugs. Version 2 also additional features like an mmu, ddr memory,
Ethernet and icap. Also version 2 uses the new xilinx pr flow in ise 12 and higher.
SInce i have the ISE 12.4 and i have no problem for the board i will move to the V2.
So i just started to folow the tutorial . For the section Implementing non partial Reconfigurable version , i have two question:
1. For the files that i have to add to the project , i added the config.v decode.v , memory_define.v and mips_platform.v. Are these all the files i have to add to the project? or there is misssing files.
2. For the necessary IP CORES i have to add all the component listed in appendix C??
Thanks in advance
Config.v, etc should be added to the project directory and should be available under source\hdl\definitions. Emips_platform is the to file and should be located under source\hdl\top\platform. Yes you will need to generate the up cores in the appendix. There
more files to add but I did think it necessary to list them there. Start from platform and fill in the hierarchy.
I changed to use the emipsV2 and i have added almost all the files but i can't find the file iftocp0.v.